Novel Low Complexity Pulse-Triggered Flip-Flop for Wireless Baseband Applications

A low complexity dual-mode pulse-triggered FF design for wireless baseband processing is presented in this paper. It supports both single-edge- and double-edge-triggered operations subject to a mode select control. Due to the novelty in pulse generator design, the layout area overhead is only 8% when compared with other single-mode counterpart design. Postlayout simulations in TSMC 1P6M 0.18？μm CMOS process model also indicate that the proposed design is as efficient as its single-mode counterpart in various performance metrics. 1. Introduction Flip-flops (FFs) are the basic storage elements used extensively in all kinds of digital designs. In particular, digital designs nowadays often adopt intensive pipelining techniques and employ many FF-rich modules such as register file and shift register. FFs thus contribute a significant portion of gate count to the overall system design. To reduce the circuit complexity, pulse-triggered FFs have been considered as a popular alternative to the conventional master-slave-based FF these days. A pulse-triggered FF consists of a pulse generator (also called transition detector) for strobe signals and a latch for data storage. Since the pulses are generated on the transition edges of the clock signal and very narrow in pulse width, the latch acts like an edge-triggered FF. The circuit complexity of a pulse-triggered FF is thus greatly simplified since only one latch, as opposed to two latches in master-slave configuration, is needed. It can thus provide higher toggle rate than the conventional FF can and is found useful in high speed applications. Another advantage of pulse-triggered FFs is that they allow time borrowing across cycle boundaries and feature zero or even negative setup time [1–3]. Pulse-triggered FFs (P-FFs) can be classified into two types, that is, implicit and explicit, depending on the implementation of pulse generator [4]. In implicit type P-FF, the pulse generator is a built-in logic of the latch design, and no explicit pulse signals are generated. In explicit type P-FF, the designs of pulse generator and the latch are separate. Although implicit pulse generation is often considered as more power efficient, the lengthened signal discharge path in latch design leads to inferior timing characteristics. In design practices, one pulse generation circuitry can be shared among FFs within the same register in explicit pulse generation. This gives the explicit type designs advantages in both circuit complexity and power consumption. In this paper, we will therefore focus on the explicit type designs only.