Parity-preserving reversible circuits are gaining importance for the development of fault-tolerant systems in nanotechnology. On the other hand, Quantum-dot Cellular Automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. This work targets design of reversible ALU (arithmetic logic unit) in QCA (Quantum-dot Cellular Automata) framework. The design is based on the fault tolerant reversible adders (FTRA) introduced in this paper. The proposed fault tolerant adder is a parity-preserving gate, and QCA implementation of FTRA achieved 47.38% fault-free output in the presence of all possible single missing/additional cell defects. The proposed designs are verified and evaluated over the existing ALU designs and found to be more efficient in terms of design complexity and quantum cost. 1. Introduction Reversible logic has attractive perspective of constructing digital devices that can realize computing unit with almost zero power dissipation. Landauer [1] proved that for irreversible computations, each bit of information loss generates joules of heat energy. The energy required for a binary transition is given by SNL (Shannon-Von Neumann-Landauer) expression in [1] as follows: where is Boltzmann constant and ？K. This is the minimum energy to process a bit. Bennett [2] showed that a zero power dissipation in logic circuit is possible only if the circuit is composed of reversible logic gates. Since QCA circuits are clocked information preserving systems, the energy dissipation of QCA circuits can be significantly lower than . This feature favours the introduction of QCA technology in reversible logic design. Though, reversibility recovers bit loss, but it is not able to detect bit error in circuit. Fault-tolerant reversible circuits are capable of preventing errors at outputs. If the system itself made of fault-tolerant components, then the detection and correction of faults become easier and simple. In communication and many other systems, fault tolerance is achieved by parity. Therefore, parity-preserving reversible circuits will be the future design trends to the development of fault-tolerant reversible systems in nanotechnology. On the other hand, QCA (Quantum-dot Cellular Auto-mata) is considered to be promising in the field of nanotechnology due to their extremely small sizes and ultralow-power consumption [3]. The QCA is based on encoding binary information in the charge configuration of quantum-dot cells. The interaction between cells is coulombic and provides the necessary computing power. The fundamental unit of
References
[1]
R. Landauer, “Irreversibility and heat generation in the computing process,” IBM Journal of Research and Development, vol. 5, no. 3, pp. 183–191, 1961.
[2]
C. H. Bennett, “Logical reversibility of computation,” IBM Journal of Research and Development, vol. 17, no. 6, pp. 525–532, 1973.
[3]
C. S. Lent, P. D. Tougaw, W. Porod, and G. H. Bernstein, “Quantum cellular automata,” Nanotechnology, vol. 4, no. 1, pp. 49–57, 1993.
[4]
Z. Guan, W. Li, W. Ding, Y. Hang, and L. Ni, “An arithmetic logic unit design based on reversible logic gates,” in Proceedings of the 13th IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PacRim '11), pp. 925–931, August 2011.
[5]
M. Morrison and N. Ranganathan, “Design of a reversible ALU based on novel programmable reversible logic gate structures,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI '11), pp. 126–131, Washington, DC, USA, July 2011.
[6]
Y. Syamala and A. V. N. Tilak, “Reversible arithmetic logic unit,” in Proceedings of the 3rd International Conference on Electronics Computer Technology (ICECT '11), pp. 207–211, April 2011.
[7]
J. W. Bruce, M. A. Thornton, L. Shivakumaraiah, P. S. Kokate, and X. Li, “Efficient adder circuits based on a conservative reversible logic gate,” in Proceedings of IEEE Symposium on VLSI, pp. 83–88, Washington, DC, USA, 2002.
[8]
M. Haghparast and K. Navi, “A novel fault tolerant reversible gate for nanotechnology based systems,” American Journal of Applied Sciences, vol. 5, no. 5, pp. 519–523, 2008.
[9]
Md. S. Islam, M. M. Rahman, Z. Begum, and M. Z. Hafiz, “Efficient approaches for designing fault tolerant reversible carry look-ahead and carry-skip adders,” MASAUM Journal of Basic and Applied Sciences, vol. 1, no. 3, pp. 354–360, 2009.
[10]
S. K. Mitra and A. R. Chowdhury, “Minimum cost fault tolerant adder circuits in reversible logic synthesis,” in Proceedings of the 25th International Conference on VLSI Design (VLSID '12), pp. 334–339, January 2012.
[11]
K. Walus, T. J. Dysart, G. A. Jullien, and R. A. Budiman, “QCADesigner: a rapid design and simulation tool for quantum-dot cellular automata,” IEEE Transactions on Nanotechnology, vol. 3, no. 1, pp. 26–31, 2004.
[12]
T. Toffoli, “Reversible computing,” in Proceedings of the 7th Colloquium on Automata, Languages and Programming, pp. 632–644, Springer, London, UK, 1980.
[13]
M. Perkowski, M. Lukac, P. Kerntopf et al., “A hierarchical approach to computer-aided design of quantum circuits,” in Proceedings of the 6th International Symposium on Representations and Methodology of Future Computing Technology, pp. 201–209, 2003.
[14]
B. Parhami, “Fault-tolerant reversible circuits,” in Proceedings of the 40th Asilomar Conference on Signals, Systems, and Computers (ACSSC '06), pp. 1726–1729, November 2006.
[15]
X. Ma and F. Lombardi, “Fault tolerant schemes for QCA systems,” in Proceedings of the 23rd IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT '08), pp. 236–244, October 2008.
[16]
M. B. Tahoori, J. Huang, M. Momenzadeh, and F. Lombardi, “Testing of quantum cellular automata,” IEEE Transactions on Nanotechnology, vol. 3, no. 4, pp. 432–442, 2004.
[17]
M. Momenzadeh, M. Ottavi, and F. Lombardi, “Modeling QCA defects at molecular-level in combinational circuits,” in Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT '05), pp. 208–216, October 2005.
[18]
M. Ottavi, L. Schiano, F. Lombardi, and D. Tougaw, “HDLQ: a HDL environment for QCA design,” Journal on Emerging Technologies in Computing Systems, vol. 2, no. 4, pp. 243–261, 2006.
