Dynamic logic is a well-known logic style which is widely used in digital electronics. A mixed dynamic/static full adder cell is presented in this paper with the aim of reaching high efficiency. The midoutputs are obtained from a Multi-output dynamic module. Then, a multiplexer generates final outputs in the static part. Several conventional and state-of-the-art dynamic adders are also surveyed and compared in the paper. All circuits are simulated by HSPICE with 32？nm CNFET technology. The proposed design is the fastest dynamic adder cell. In addition, it has approximately 5% higher efficiency in terms of PDP than the second most high-performance cell, which is DDCVS. 1. Introduction In today’s VLSI circuit designs, the increasing demand for high-speed and low-power structures can be addressed at different design levels including design methodology and fabrication technology. From the technological view, many fundamental drawbacks of metal-oxide semiconductor (MOS) technology such as short-channel effects, high leakage power dissipation, large parametric variations, and reduced gate control make numerous challenges and difficulties for the near future generation of integrated circuits (ICs) [1]. In order to overcome the mentioned problems, some nanoscale devices such as single-electron transistor (SET) [2], quantum-dot cellular automata (QCA) [3], and carbon nanotube field effect transistor (CNFET) [4] have recently been presented in the literature to be employed in nanoscale digital electronics. According to the Moor’s law, miniaturization and optimization of transistors to the nanoranges are the most dominant obstacles of silicon-based technology. Hence, downsizing of the conventional silicon-based devices will reach its limit at the gate length of 5？nm around the year 2020 [5]. CNFET, which is one of the most promising devices among the emerging nanotechnologies, turned out to be an alternative technology to implement switches with miniaturized dimensions. Based on comprehensive investigations on the characteristics of CNFETs, they have high superior properties such as close structural and behavioral similarities to the current CMOS devices, reusability of fabrication process, and excellent current handling capabilities with high thermal conductivity [6]. As the threshold voltage of the CNFET is proportional to the inverse of the diameter of CNT ( ) [4], different threshold voltages can be achieved by changing the diameter of CNFETs. The relationship is shown in (1) where parameter a (≈ 0.249？nm) is the carbon-to-carbon atom distance, (≈ 3.033？eV) is
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