This paper presents a comprehensive review and a comparative study of various hardware/FPGA implementations of Sobel edge detector and explored different architectures for Sobel gradient computation unit in order to show the various trade-offs involved in choosing one over another. The different architectures using pipelining and/or parallelism (key methodologies for improving the performance/frame rates) are explored for gradient computation unit in Sobel edge detector. How the different architectures affected performance (in terms of video frame rate and image size) and area (in terms of FPGA resources usages) has been demonstrated. By exploiting the trade-offs between video frame rate, image size, and FPGA resources a designer should be able to find an optimal architecture for a given application. 1. Introduction Edge detection, one of the fundamental and most important problems of lower level image processing, plays a very important role in the realization of a complete vision based understanding/monitoring system for automatic scene analysis/monitoring [1]. Edges provide significant and important information related to objects present in the scene. This information helps in achieving higher level objectives like segmentation, object recognition, scene analysis, and so forth. Edges in digital images are defined as the image positions/points where the intensity/brightness of two neighboring pixels is significantly different. Many robust and complex approaches for the edge detection have been proposed in scientific literature. These give different responses and details for same input images. Sobel operator based edge detection technique is very popular and intensively used in many applications due to its ability to counteract the noise sensitivity over simple gradient operators and its easier implementations [2]. Very different approaches have been used in the literature for Sobel operator based edge detection algorithm. These range from use of general purpose processors or special purpose digital signal processors or graphics processing units (GPUs) using compute unified device architecture (CUDA) to application specific integrated circuits (ASICs) or applications specific instruction set processors (ASIPs) or even programmable logic devices like field programmable gate arrays (FPGAs). FPGAs provide real-time performance, limit the extensive design work and time required for ASICs, and provide possibility to perform algorithmic changes in later stages of system development. These features make FPGAs a suitable choice for implementing image processing
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