This paper presents novel floating gate MOSFET (FGMOS) based differential voltage squarer using FGMOS characteristics in saturation region. The proposed squarer is constructed by a simple FGMOS based squarer and linear differential voltage attenuator. The squarer part of the proposed circuit uses one of the inputs of two-input FGMOS transistor for threshold voltage cancellation so as to implement a perfect squarer function, and the differential voltage attenuator part acts as input stage so as to generate the differential signals. The proposed circuit provides a current output proportional to the square of the difference of two input voltages. The second order effect caused by parasitic capacitance and mobility degradation is discussed. The circuit has advantages such as low supply voltage, low power consumption, and low transistor count. Performance of the circuit is verified at ±0.75？V in TSMC 0.18？μm CMOS, BSIM3, and Level 49 technology by using Cadence Spectre simulator. 1. Introduction Technology scaling and growing demand of portable electronic equipments have motivated the researchers towards the design of low voltage and low power analog signal processing circuits. Low supply voltage increases the battery lifetime and hence reduces the power consumption of the portable equipment. Various low-voltage lowpower design techniques reported in literatures include subthreshold MOSFETs, level shifters, self-cascode, bulk-driven, and FGMOS techniques [1–10]. Among these, FGMOS concept has gained prime importance due to its ability to reduce or remove the threshold voltage requirement of the circuit. Scaling of transistor dimensions has motivated the designers towards the design of low voltage nonlinear CMOS circuits. Voltage squarer is one of the most versatile nonlinear blocks that find application in several fields like neural and image signal processing [11–18]. It can be used to implement various nonlinear circuits such as multipliers, balanced modulators, and phase comparators. Analog hardware implementation of these blocks offers advantage of reduced silicon area and low power consumption. CMOS squarer circuit based on cross-coupled differential pair has been proposed in [11] but the circuit is complex and has large supply voltage requirement. Squarer with low supply voltage and high rejection of common-mode variations has been proposed in [12] and [13], respectively, but again these circuits require large number of transistors. Recently, the squarer topology using NMOS transistor has been proposed in [16] but it requires positive and negative bias
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