Design of High-Speed Adders for Efficient Digital Design Blocks

The core of every microprocessor and digital signal processor is its data path. The heart of data-path and addressing units in turn are arithmetic units which include adders. Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well suited for VLSI implementations. This paper involves the design and comparison of high-speed, parallel-prefix adders such as Kogge-Stone, Brent-Kung, Sklansky, and Kogge-Stone Ling adders. It is found that Kogge-Stone Ling adder performs much efficiently when compared to the other adders. Here, Kogge-Stone Ling adders and ripple adders are incorporated as a part of a lattice filter in order to prove their functionalities. It is seen that the operating frequency of lattice filter increases if parallel prefix Kogge-Stone Ling adder is used instead of ripple adders since the combinational delay of Kogge-Stone Ling adder is less. Further, design and comparison of different tree adder structures are performed using both CMOS logic and transmission gate logic. Using these adders, unsigned and signed comparators are designed as an application example and compared with their performance parameters such as area, delay, and power consumed. The design and simulations are done using 65？nm CMOS design library. 1. Introduction Binary addition is one of the most primitive and most commonly used applications in computer arithmetic. A large variety of algorithms and implementations have been proposed for binary addition [1–3]. Parallel-prefix adder tree structures such as Kogge-Stone [4], Sklansky [5], Brent-Kung [6], Han-Carlson [7], and Kogge-Stone using Ling adders [8, 9] can be used to obtain higher operating speeds. Parallel-prefix adders are suitable for VLSI implementation since they rely on the use of simple cells and maintain regular connections between them. VLSI integer adders are critical elements in general purpose and digital-signal processors since they are employed in the design of Arithmetic-Logic Units, floating-point arithmetic data paths, and in address generation units. Moreover, digital signal processing makes extensive use of addition in the implementation of digital filters, either directly in hardware or in specialized digital signal processors (DSPs). In integer addition, any decrease in delay will directly relate to an increase in throughput. In nanometer range, it is very important to develop addition algorithms that provide high performance while reducing power consumption. The requirements of the adder are that it should be primarily fast and secondarily efficient in