MOS Current Mode Logic with Capacitive Coupling

A new MOS current mode logic (MCML) style exhibiting capacitive coupling to enhance the switching speed of the digital circuits is proposed. The mechanism of capacitive coupling and its effect on the delay are analytically modeled. SPICE simulations to validate the accuracy of the analytical model have been carried out with TSMC 0.18？μm CMOS technology parameters. Several logic gates such as five-stage ring oscillator, NAND, XOR2, XOR3, multiplexer, and demultiplexer based on the proposed logic style are implemented and their performance is compared with the conventional logic gates. It is found that the logic gates based on the proposed MCML style lower the delay by 23 percent. An asynchronous FIFO based on the proposed MCML style has also been implemented as an application. 1. Introduction The rapid advances in the VLSI technology have led to the development of high-resolution mixed-signal applications. These applications demand high performance digital circuits to be integrated with analog circuitry on the same chip. MOS current mode logic (MCML) style has been widely used in digital circuits design for mixed-signal applications as they provide an analog friendly environment due to the low switching noise [1–4]. MCML circuits exhibit high switching speed, high noise immunity and better power efficiency at high operating frequencies along with a drawback of static power consumption [5–8]. In mixed-signal applications, the digital circuits are extensively used in the realization of digital signal processor functional units such as finite impulse response (FIR) filter and FFT module. The functional units are required to perform computations at high speed to efficiently use the bandwidth in communication systems which is also increasing. Therefore it is necessary to improve the speed of conventional MCML circuits. In this paper, a new MCML style with capacitive coupling that increases the switching speed of the circuits is proposed. The paper first presents a brief introduction to conventional MCML style in Section 2. Thereafter, the architecture of the MCML style with capacitive coupling is proposed in Section 3. The mechanism of capacitive coupling is explained, and an expression for the delay is derived. The theoretical propositions are validated through SPICE simulations using TSMC 0.18？μm CMOS technology parameters in Section 4. The simulation results of several logic gates and an asynchronous FIFO are also presented in the same section. Finally, the conclusions are drawn in Section 5. 2. Conventional MCML Circuits A conventional MCML circuit