Modelling, Design, and Performance Comparison of Triple Gate Cylindrical and Partially Cylindrical FinFETs for Low-Power Applications

The FinFETs recently have been the rallying point for the engineers as far as the development of the technology is concerned. The authors here have tried successfully to compare the performance of 30？nm conventional triple gate (Conv) FinFET structure with that of partially cylindrical (PC) FinFET. In PC-FinFET the fin is divided into two regions. Region I is partially cylindrical and has curvature of half of the fin width, and Region II is like a conventional FinFET (having flat region). The results show that there is considerable improvement in Ion, Ioff, and subsequent suppression of short channel effects, that is, subthreshold slope, DIBL, self heating effect, and so forth. The improvement has also been felt in series resistance in PC-FinFET as compared to C-FinFET. It is noteworthy also to mention that in PC-FinFET the corner of fin is rounded thus reducing the side wall area which further reduces the gate capacitance reducing the intrinsic delay. The DC and transient analysis of CMOS inverter using C-FinFET and PC-FinFET have been done which shows that PC-FinFET inverter has reduced propagation delay as compared to C-FinFET. 1. Introduction In recent days the pace of scaling of MOSFETs has slowed down due to the number of reasons one being the short channel effects (SCEs) like drain-induced barrier lowering (DIBL), threshold voltage roll off, increase in subthreshold slope, increment in off state current, and so forth. Therefore, in order to continue further scaling of the devices we require better suppression of (SCE) short channel effect and unconventional structures such as multigate devices [1]. These multigate FinFETs are very promising alternative to planner devices. In sub 50？nm gate length regime, the triple gate FinFET is one of the best alternatives to planner devices. In a trigate transistor, the gate surrounds the channel from all the three sides with three gates Top, Front, and Back gates as shown in Figure 2; the structure of the type mentioned has much better control over the channel. The width (Weff) of a trigate transistor is the (sum of all the three sides), that is, (twice the fin height) + the fin width ( ). The stronger control decreases the subthreshold leakage, threshold voltage roll off, and off state current which makes the scaling possible to meet the ITRS trends [2]. Further, the triple gate FinFET has reduced the doping concentration required in the channel to the extent of 1015/cm3. However, variation in the height and width of the trigate is now an issue and needs to be tightly controlled. In FinFETs, It has been