A General Design Methodology for Synchronous Early-Completion-Prediction Adders in Nano-CMOS DSP Architectures

Synchronous early-completion-prediction adders (ECPAs) are used for high clock rate and high-precision DSP datapaths, as they allow a dominant amount of single-cycle operations even if the worst-case carry propagation delay is longer than the clock period. Previous works have also demonstrated ECPA advantages for average leakage reduction and NBTI effects reduction in nanoscale CMOS technologies. This paper illustrates a general systematic methodology to design ECPA units, targeting nanoscale CMOS technologies, which is not available in the current literature yet. The method is fully compatible with standard VLSI macrocell design tools and standard adder structures and includes automatic definition of critical test patterns for postlayout verification. A design example is included, reporting speed and power data superior to previous works. 1. Introduction Fast integer adders are an essential component of most DSP datapaths. Synchronous early-completion-prediction adders (ECPAs) [1], also known as variable-latency adders [2], have been introduced for high clock rate and high-precision datapaths, as they allow single-cycle operations even if the clock period is shorter than the worst-case carry propagation delay. Thanks to the data dependency of actual carry chain propagation, the occurrence of multicycle operations can be maintained statistically rare, thus allowing an overall speed improvement. The industrial effectiveness of the idea was first proven by the design of a full-custom ECPA unit for a DSP datapath at Toshiba Labs [1]. The logic foundation of that adder is shown in [3]. An extension to multiply unit design has been shown in [4]. The works in [2] and [5] have recently pointed out the potentials of variable-latency adder units in nano-CMOS addition units, for reducing average leakage power consumption and improving robustness to NTBI faults occurring in nano-scale technologies. An ECPA consists of a conventional adder plus a completion-prediction logic unit (Figure 1). The prediction unit estimates the actual critical path length in the adder depending on the operand values and hence the cycle count of the operation for the target cycle time. This approach differs from asynchronous completion detection units [6–8], as it is based on a totally synchronous scheme. From the design point of view, the logic specification of the prediction function depends on the target cycle time and on the estimation of the variable completion time of the adder, in order to define the cycle count output. Moreover, the speed of the prediction unit is critical,