Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL

Asynchronous adiabatic logic (AAL) is a novel lowpower design technique which combines the energy saving benefits of asynchronous systems with adiabatic benefits. In this paper, energy efficient full adder using double pass transistor with asynchronous adiabatic logic (DPTAAL) is used to design a low power multiplier. Asynchronous adiabatic circuits are very low power circuits to preserve energy for reuse, which reduces the amount of energy drawn directly from the power supply. In this work, an multiplier using DPTAAL is designed and simulated, which exhibits low power and reliable logical operations. To improve the circuit performance at reduced voltage level, double pass transistor logic (DPL) is introduced. The power results of the proposed multiplier design are compared with the conventional CMOS implementation. Simulation results show significant improvement in power for clock rates ranging from 100？MHz to 300？MHz. 1. Introduction Over the past few decades, low power design solution has steadily geared up the list of researcher’s design concerns for low power and low noise digital circuits to introduce new methods to the design of low power VLSI circuits. Moore’s law describes the requirement of the transistors for VLSI design which gives the experimental observation of component density and performance of integrated circuits, which doubles every two years. Transistor count is a primary concern which largely affects the design complexity of many function units such as multiplier and arithmetic logic unit (ALU). The significance of the digital computing lies in the multiplier design. The multipliers play a significant role in arithmetic operations in DSP applications. Recent developments in processor designs also focus on low power multiplier architecture usage in their circuits. Two significant yet often conflicting design criteria are power consumption and speed. Taking into consideration these constraints, the design of low power multiplier is of great interest. As reported in [1], to get the best power and area requirements of the computational complexities in the VLSI circuits, the length and width of transistors are shrunk into the deep submicron region, handled by process engineering. In recent years, the literatures have identified several types and designs of adiabatic circuits. For instance, 2N2N2P, PFAL, pass transistor adiabatic logic, clocked adiabatic lLogic, improved pass-gate adiabatic logic, and adiabatic differential switch Logic were designed and achieved considerable energy savings, compared with conventional CMOS design [3–9].