High-Accuracy Programmable Timing Generator with Wide-Range Tuning Capability

In this paper, a high-accuracy programmable timing generator with wide-range tuning capability is proposed. With the aid of dual delay-locked loop (DLL), both of the coarse- and fine-tuning mechanisms are operated in precise closed-loop scheme to lessen the effects of the ambient variations. The timing generator can provide sub-gate resolution and instantaneous switching capability. The circuit is implemented and simulated in TSMC 0.18？μm 1P6M technology. The test chip area occupies 1.9？mm2. The reference clock cycle can be divided into 128 bins by interpolation to obtain 14？ps resolution with the clock rate at 550？MHz. The INL and DNL are within ？0.21~+0.78 and ？0.27~+0.43 LSB, respectively. 1. Introduction Time is one of the important properties of the nature. Timing generators, a.k.a. delay generators, are used to produce accurate clock signals with adjustable timing which can be widely applied in the instrumentation and chip system [1–5], like IC testers, pulse generators, logic analyzers, oscilloscopes, and time-to-digital converters. With the advancing progress in IC technology, the timing generator can be implemented and integrated as the analog front-end circuitry with other digital circuitry inside the same chip. In recent designs, delay-locked loops (DLLs) are suitable to provide the timing function in all time issues. And DLLs can also offer precise timing reference signals to ensure the system operation properly. For most timing generators using DLL often providing the resolution of single buffer gate delay, the sub-gate resolution is acquired via gate delay difference [1], external control [2], or phase interpolation [5]. However, these approaches work in open-loop manners. Thus, the open-loop circuitry is very sensitive to ambient variations caused by process, voltage, and temperature. In this paper, a high-accuracy programmable timing generator with wide-range tuning capability is proposed to offer the sub-gate resolution with closed-loop control which alleviates the ambient impacts. With the aid of dual DLL, the delay resolution can be monitored and regulated continuously in switching the timing setting instantaneously. 2. Circuit Architecture and Principle of Operation The proposed circuit architecture and timing operation of the programmable timing generator are depicted in Figure 1. Since the aim of the proposed circuit is to divide the clock cycle of the input reference clock into different phases by digital controlled codes, the timing generator is constructed by coarse and fine stages to generate resolutions which are one buffer