Design a Bioamplifier with High CMRR

A CMOS amplifier with differential input and output was designed for very high common-mode rejection ratio (CMRR) and low offset. This design was implemented by the 0.35？μm CMOS technology provided by TSMC. With three stages of amplification and by balanced self-bias, a voltage gain of 80？dB with a CMRR of 130？dB was achieved. The related input offset was as low as 0.6？μV. In addition, the bias circuits were designed to be less sensitive to the power supply. It was expected that the whole amplifier was then more independent of process variations. This fact was confirmed in this study by simulation. With the simulation results, it is promising to exhibit an amplifier with high performances for biomedical applications. 1. Introduction For biomedical applications, a voltage amplifier with a gain of 80？dB and a high CMRR is required as a building block in front-end subsystems [1, 2]. Since the voltage level of physiologic signals at the front-end subsystem is very weak, processes for analog signals usually include several steps of amplification, filtering, offset adjustment, and electrical conditioning. After suitable processing, the signal will then be large enough and effectively suitable for analog-to-digital conversion at later stages [3–5]. In considering the physiological signals extracted from human bodies, the amplitude of an electrocardiographic (ECG) signal is usually less than 100？μV. Such value is very weak as compared to the noise floor and imperfection of the commonly used operational amplifiers (OPAs). An instrumentation amplifier (IA) is usually employed to achieve the required performances. In addition to the requirement of high voltage gain in constructing the amplifiers for an IA, another important requirement for the amplifiers is CMRR. According to the recommendations of Association of the Advancement of Medical Instrumentation (AAMI), CMRR is required to be higher than 90？dB with the open-loop voltage gain higher than 80？dB. In this study, the 0.35？μm CMOS technology of TSMC was employed in designing a high performance amplifier. In our study, a high-voltage-gain amplifier was tried with a self-biasing technique to have a high CMRR and low input offset and to be less sensitive to process variations. The simulation was performed based on the models supported by Chip Implementation Center (CIC). The related results will be illustrated. 2. Design Details 2.1. Design of the Differential Amplifier For the purposes of high CMRR and low offset at the input, differential configuration with a symmetrical floor planning in layout will be