Design Example of Useful Memory Latency for Developing a Hazard Preventive Pipeline High-Performance Embedded-Microprocessor

The existence of structural, control, and data hazards presents a major challenge in designing an advanced pipeline/superscalar microprocessor. An efficient memory hierarchy cache-RAM-Disk design greatly enhances the microprocessor's performance. However, there are complex relationships among the memory hierarchy and the functional units in the microprocessor. Most past architectural design simulations focus on the instruction hazard detection/prevention scheme from the viewpoint of function units. This paper emphasizes that additional inboard memory can be well utilized to handle the hazardous conditions. When the instruction meets hazardous issues, the memory latency can be utilized to prevent performance degradation due to the hazard prevention mechanism. By using the proposed technique, a better architectural design can be rapidly validated by an FPGA at the start of the design stage. In this paper, the simulation results prove that our proposed methodology has a better performance and less power consumption compared to the conventional hazard prevention technique. 1. Introduction In current computer architecture, the multiple-instruction (pipeline, superscalar) microprocessors are proposed to improve the efficiency of a single-instruction microprocessor. There are usually four stages (instruction fetch, decode, execute, and writeback) adopted in a multiple-cycle processor. The CPI (cycle per instruction) value of the pipeline (multiple-instruction) microprocessor is several times larger than that of a single-instruction microprocessor. Generally, the pipeline architecture is combined with RISC (reduced instruction set computer) methodology to design high performance processors. Pipeline microprocessor hazards occur when multiple instructions are executed. The pipeline architectural hazards that are introduced in [1, 2] make the program instructions unable to be parallely executed. In general, there are three types of hazards: structure, control, and data hazards. A structural hazard means that the hardware components (resources) are insufficient to support the execution of the pipeline instructions in the same clock cycle. The frequently occurring case of the hardware components conflicting when sharing the single port memory means that they are unable to support the read/write operation at the same time. The second type of hazard is termed a control hazard, which arises from the present executed instruction’s inability to make decisions because this instruction decision making should rely on the results from the next following executed