Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs

We are examining different configurations and circuit topologies for arithmetic components such as adder and compressor circuits using both symmetric and asymmetric work-function FinFETs. Based on extensive characterization data, for the carry generation of a mirror full adder using symmetric devices, both leakage current and delay are decreased by 25% and 50%, respectively, compared to results in the literature. For the 14-transistor (14T) full adder topology, both leakage and delay are decreased by 23% and 29%, respectively, compared to the mirror topology. The 14T adder topology, using asymmetric devices without any additional power supply, achives reduction in leakage current by 85% with a small degradation of 7% in delay. The compressor circuits, using asymmetric devices for one of the proposed configurations, achieve reduction in both leakage current and delay by 86% and 4%, respectively. All simulations are based on a 25？nm FinFET technology using the University of Florida UFDG model. 1. Introduction The demand for smaller and faster portable electronic equipment has forced the semiconductor technology to a sharp reduction in the minimum feature size from the micro- to the nanometer regime [1]. The advancement in process technologies has paved the way to the realization of highly complex systems on a single device targeting real-time high speed applications such as wireless communication and computing. With extremely high level of integration in the nanodomain of planar CMOS technology, the subthreshold leakage current is becoming a major concern for system designers due to the reduction in the threshold voltage of devices as well as reductions in other device parameters to maintain device scalability rules. This situation becomes significant in sub-22？nm bulk CMOS technology due to its very poor channel electrostatic potential which leads to degraded short-channel behaviour and high leakage current [2]. FinFETs overcome these problems with a stronger control of the channel potential by using two gates wrapped around the fin [2]. Until now, several studies have been performed on FinFET logic circuits in [2–4] which applied back gate biasing techniques to reduce leakage current. However, much less studies and analyses have been conducted on FinFET-based arithmetic functions. In [4], a full adder based on mirror architecture, using double-gate FinFET, has been proposed and analyzed. The results from this work will be used later on in our paper as a basis for our comparison with our proposed architectures. The goal of this paper is to develop