In digital communications, an usual reception chain requires many stages of digital signal processing for filtering and sample rate reduction. For satellite on board applications, this need is hardly constrained by the very limited hardware resources available in space qualified FPGAs. This short paper focuses on the implementation of a dual chain of 14 stages of cascaded half band filters plus 2？:？1 decimators for complex signals (in-phase and quadrature) with minimal hardware resources, using a small portion of an UT6325 Aeroflex FPGA, as a part of a receiver designed for a low data rate command and telemetry channel. 1. Introduction In digital receivers used in satellite applications [1], after conversion to an intermediate frequency (IF) and filtering, a common approach is to shift the signal to baseband [2]. Since the IF spectrum is not symmetrical, the translation to baseband creates a complex signal [3] composed of in-phase (I) and quadrature (Q) components; this complex signal is then band-limited by successive steps of filters and decimators before data detection. Many alternatives exist for filters and decimators, like cascaded integrator comb (CIC or Hogenauer) filters [4–6], cyclotomic polynomial filters [7–9], or polyphase decimators [10, 11]. These algorithms are difficult to be implemented using space qualified FPGAs. These devices are designed to support high levels of ionizing radiation, composed by alpha particles, protons, and heavy ions, so they use technologies three or more times bigger in size details than current commercial FPGA devices, and main datasheet parameters are total accumulated radiation (TID) dose in krads and tolerance to single event upsets (SEU) and single event latchup (SEL) in MeV·cm2/mg; packages are also limited in size and weight to tolerate high accelerations and wide temperature operating ranges. As a consequence of these constraints, space-qualified FPGAs are much slower and many times smaller in number of logical cells than commercial devices, and implementation efforts are directed to low complexity solutions [11, 12], trying to avoid multipliers or complex arithmetic operations. The design described in this paper is focused on the implementation of a block of two chains of 14 filters and decimators used for the reception of the low data rate (4？kbps) spaceflight tracking and data network command channel [13], transmitted from ground to a low earth orbit satellite (LEO), and the paper details the hardware improvements used for efficient filtering processes. 2. The Communications Link A LEO satellite with
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