Systematic Design Methodology of a Wideband Multibit Continuous-Time Delta-Sigma Modulator

Systematic design of a low power, wideband and multi-bit continuous-time delta-sigma modulator (CTDSM) is presented. The design methodology is illustrated with a 640？MS/s, 20？MHz signal bandwidth 4th order 2-bit CTDMS implemented in 0.18？μm CMOS technology. The implemented design achieves a peak SNDR of 65.7？dB and a high dynamic range of 70？dB while consuming only 19.7？mW from 1.8？V supply. The design achieves a FoM of 0.31？pJ/conv. Direct path compensation is employed for one clock excess loop delay compensation. In the feedforward topology, capacitive summation using the last opamp eliminates extra summation opamp. 1. Introduction Delta-sigma modulators embed low-resolution analog-to-digital converter in a feedback loop. The use of feedback and high oversampling pushes the quantization noise out of the band of interest and thereby provides a high in-band resolution. Delta-sigma modulator is well suitable for a high-resolution data conversion because a moderate accuracy of passive components is required. Recently, continuous-time delta-sigma modulator has brought tremendous attention because of its exceptional features such as inherent antialiasing filter (AAF), relaxed gain-bandwidth requirement on active elements resulting in a low-power consumption compared to its counterpart discrete-time delta-sigma modulator [1, 2]. Low-power consumption is the key for a CTDSM. In [3], the design methodology for a multibit modulator with two-step quantizer is presented. However, the optimization of the peak SNR and the maximum stable amplitude is not taken into consideration. Also, excess loop delay compensation is for more than one clock, where, to achieve higher resolution, higher bit quantizer should be used. These all increase the design methodology complexity and are not simple to adopt for designers. To keep the design simple and the insight intact, we implement one-step quantizer with excess loop delay compensation for one clock. In [4], the optimal design methodology of a higher-order continuous-time wideband delta-sigma modulator is presented. However, this methodology requires summation amplifier and hence consumes higher power. In our approach, the summation amplifier is eliminated by using capacitive summation with last integrator’s amplifier and this makes design simpler and saves significant power. Also, in [4] SNR and phase margin are optimized which could be replaced to simpler way to optimize the peak SNR and the maximum stable amplitude which are more obvious parameters. Recent development in wireless communication standard demands a wideband