Design Multipurpose Circuits with Minimum Garbage Outputs Using CMVMIN Gate

Quantum-dot cellular automata (QCA) suggest an emerging computing paradigm for nanotechnology. The QCA offers novel approach in electronics for information processing and communication. QCA have recently become the focus of interest in the field of low power nanocomputing and nanotechnology. The fundamental logic elements of this technology are the majority voter (MV) and the inverter (INV). This paper presents a novel design with less garbage output and minimum quantum cost in nanotechnology. In the paper we show how to create multipurpose reversible gates. By development of suitable gates in logic circuits as an example, we can combine MFA and HS in one design using CMVMIN gate. We offer CMVMIN gate implementations to be used in multipurpose circuit. We can produce concurrent half adder/subtractor and one bit comparator in one design using reversible logic gates and CMVMIN gates. Also, a decoder from recent architecture has been shown independently. We investigate the result of the proposed design using truth table. A significant improvement in quality of the calculated parameters and variety of required outputs has been achieved. 1. Introduction This heat dissipation extremely reduces the performance and lifetime of the circuits. The solution is to use revolutionary technology which enables extremely low power consumption and heat waste in computing [1]. Reversible logic gates are extensively known to be compatible with future computing technologies which approximately dissipate zero heat [2]. Reversible are the circuits or the gates that have the same number of inputs and outputs and have one-to-one mappings between vectors of inputs and outputs; thus, the vector of the input states can be uniquely reconstructed from the vector of the output states [3]. The QCA (Quantum-dot cellular automata) are considered to be the promising technology for future generation ICs that overcome the limitations of CMOS. The fundamental unit of QCA based design is the 3-input majority gate (majority voter, MV) and the inverter. The wide acceptance of QCA in logic design attracts researchers to explore new universal gate structures targeting cost effective realization [4]. Existing synthesis tools do not make efficient use of MV in technology mapping for synthesis of logic designs. Even for arithmetic circuits, in which there should be perfect matches for the MV, the synthesis tools rarely find any matches [5]. This satisfies the requirement of optimum logic gates as well as minimum number of garbage outputs in an energy efficient design [6]. We illustrate CMVMIN gate