A new low-voltage MOS current mode logic (MCML) topology for D-latch is proposed. The new topology employs a triple-tail cell to lower the supply voltage requirement in comparison to traditional MCML D-latch. The design of the proposed MCML D-latch is carried out through analytical modeling of its static parameters. The delay is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption. The proposed low-voltage MCML D-latch is analyzed for the two design cases, namely, high-speed and power-efficient, and the performance is compared with the traditional MCML D-latch for each design case. The theoretical propositions are validated through extensive SPICE simulations using TSMC 0.18？μm CMOS technology parameters. 1. Introduction The advances in semiconductor technology have led to the integration of high performance digital and analog circuits on the same silicon substrate. The traditional CMOS logic style does not provide an analog friendly environment due to the large switching noise [1–3]. Many alternate logic styles have been suggested in [3–6] and the reference mentioned therein. MOS current mode logic (MCML) style is the most promising one due to the lower switching noise in comparison to traditional CMOS logic style [6–9]. Also, it exhibits better power delay than the traditional CMOS logic style at high frequencies [6–15]. Therefore, MCML style is appropriate for designing high performance digital circuits wherein a D-latch is widely used as a building block in different applications such as prescalars, frequency dividers, and sequential logic circuits [16–20]. The D-latch topology given in [16–20] is referred to as traditional D-latch and is based on the series-gating approach (i.e., stacked source-coupled transistor pairs) [9] which puts a limit on the minimum power supply. The power supply may, however, be lowered by reducing the number of stacked transistor pair levels with triple-tail cell concept [21–23]. In this paper, a new low-voltage MCML D-latch is proposed. The static parameters for the proposed D-latch are analytically modeled and applied to develop a design approach. From the knowledge of the transistor sizes, the delay is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption. The proposed low-voltage multiplexer is analyzed for high-speed and power-efficient design cases. A comparison in performance of the proposed D-latch with the traditional one is carried out for all the cases. The paper first briefs the
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