We proposed and computationally analyzed a multivalued, nonvolatile SRAM using a ReRAM. Two reference resistors and a programmable resistor are connected to the storage nodes of a standard SRAM cell. The proposed 9T3R MNV-SRAM cell can store 2 bits of memory. In the storing operation, the recall operation and the successive decision operation of whether or not write pulse is required can be performed simultaneously. Therefore, the duration of the decision operation and the circuit are not required when using the proposed scheme. In order to realize a stable recall operation, a certain current (or voltage) is applied to the cell before the power supply is turned on. To investigate the process variation tolerance and the accuracy of programmed resistance, we simulated the effect of variations in the width of the transistor of the proposed MNV-SRAM cell, the resistance of the programmable resistor, and the power supply voltage with 180？nm 3.3？V CMOS HSPICE device models. 1. Introduction Power dissipation has been one of the most serious concerns in highly integrated CMOS logic circuits. For example, a leakage current’s effect becomes dominant in the standby mode. One solution is to use nonvolatile memory, which has been proposed. Typical new types of memory include ferroelectric random access memory (FeRAM), magnetoresistive RAM (MRAM), phase change RAM (PRAM), and resistivity change RAM (ReRAM). A nonvolatile SRAM (NV-SRAM) has also been developed to mitigate restriction in program cycles and to improve the access time [1–5]. The component count of the NV-SRAM is large because the nonvolatile portion must be added to the SRAM portion. The large resistivity change of ReRAM and PRAM is a superior characteristic and has been studied for multivalued nonvolatile memory [6–10]. For example, 16 separate states for multivalued storage were reported in [6]. ReRAM has been widely expected for use as the next generation of nonvolatile memory because of its superior characteristics, such as low-voltage operation, high-speed performance, and low power. This device has two switching modes: unipolar switching, in which the device depends on the pulse width and amplitude of the applied voltage, and bipolar switching, in which the device depends on the polar character. In this paper, we used a bipolar switching device that made the best use of this proposed circuit. Figure 1 shows the definition of the set and reset operations for the bipolar switching device. Set is defined as an operation conducted to change from a high resistance state (HRS) to a low resistance state
References
[1]
S. Eaton, D. Butler, M. Parris, D. Wilson, and H. Mcnellie, “A ferroelectric nonvolatile memory,” in Proceedings of the International Solid-State Circuits Conference(ISSCC '88), pp. 130–131, 1988.
[2]
S. Masui, T. Ninomiya, T. Ohkawa et al., “Design and application of ferroelectric memory based nonvolatile SRAM,” IEICE Transactions on Electronics, vol. E87-C, no. 11, pp. 1769–1776, 2004.
[3]
M. Takata, K. Nakayama, T. Izumi, T. Shinmura, J. Akita, and A. Kitagawa, “Nonvolatile SRAM based on phase change,” in Proceedings of the 21st IEEE Non-Volatile Semiconductor Memory Workshop (NVSMW '06), pp. 95–96, February 2006.
[4]
S. Yamamoto and S. Sugahara, “Nonvolatile static random access memory using magnetic tunnel junctions with current-induced magnetization switching architecture,” Japanese Journal of Applied Physics, vol. 48, no. 4, Article ID 043001, 2009.
[5]
A. Kitagawa and K. Nakayama, “Phase change nonvolatile SRAM and Resister',” in Proceedings of the 21th Symposium on Phase Change Optical information Storage (PCOS '09), pp. 33–36, 2009.
[6]
J. Maimon, E. Spall, R. Quinn, and S. Schnur, “Chalcogenide-based non-volatile memory technology,” in Proceedings of the IEEE Aerospace Conference, vol. 5, pp. 2289–2294, March 2001.
[7]
K. Nakayama, M. Takata, T. Kasai, A. Kitagawa, and J. Akita, “Pulse number control of electrical resistance for multi-level storage based on phase change,” Journal of Physics D, vol. 40, no. 17, article 009, pp. 5061–5065, 2007.
[8]
Y. Yin, K. Ota, T. Noguchi, H. Ohno, H. Sone, and S. Hosaka, “Multilevel storage in N-doped Sb2Te3-based lateral phase change memory with an additional top TiN layer,” Japanese Journal of Applied Physics, vol. 48, no. 4, Article ID 04C063, 2009.
[9]
S. Lee, J.-H. Jeong, T. S. Lee, W. M. Kim, and B.-K. Cheong, “Bias polarity dependence of a phase change memory with a Ge-doped SbTe: a method for multilevel programing,” Applied Physics Letters, vol. 92, no. 24, Article ID 243507, 2008.
[10]
Y. Han, K. Cho, and S. Kim, “Characteristics of multilevel bipolar resistive switching in Au/ZnO/ITO devices on glass,” Microelectronic Engineering, vol. 88, no. 8, pp. 2608–2610, 2011.
[11]
S. Kawabata, M. Nakura, S. Yamazaki et al., “CoOx-RRAM memory cell technology using recess structure for 128Kbits memory array,” in Proceedings of the IEEE International Memory Workshop (IMW '10), pp. 16–19, May 2010.
[12]
K. Usami and N. Ohkubo, “A design approach for fine-grained run-time power gating using locally extracted sleep signals,” in Proceedings of the 24th International Conference on Computer Design (ICCD '06), pp. 155–161, October 2006.
[13]
T. Handa, Y. Yoshimoto, K. Nakayama, and A. Kitagawa, “Novel power reduction technique for ReRAM with automatic avoidance circuit for wasteful overwrite,” Active and Passive Electronic Components, vol. 2012, Article ID 181395, 11 pages, 2012.
