Controller Design Considerations for ACM APFC Systems

This paper is concerned with performance of the current shaping network in Average Current Mode (ACM) Active Power Factor Correction (APFC) systems. Theoretical expressions for the ripple components are derived. Then, ripple interaction and impact on the current loop reference signal are investigated. A modification of the controller network is suggested that results in an improved Total Harmonic Distortion (THD). Design guidelines are suggested. The theoretical predictions were validated by simulation. 1. Introduction Over the past few years, a variety of current shaping methodologies were developed for Active Power Factor Correction (APFC) [1–3]. Each approach undertaken is a compromise in between the performance indexes and the circuit complexity and cost. The Critical Conduction Mode (CrCM) APFC operating on the CCM-DCM boundary [4–7] shapes the average input current by comparator/zero detector and is unconditionally stable. However, the natural simplicity, robustness, and stability of CrCM APFC are offset by high ripple current which cause increased conduction and core losses. Difficulties in filtering the variable frequency current ripple and poor efficiency restrict this technique to low-power and low-cost applications. Other Discontinuous Conduction Mode (DCM) based designs, which upside is simplicity suffer from similar problems exhibiting also higher harmonic distortion of the line current [8, 9]. APFC without line voltage sensing, [10–13] stands out as a robust, technologically simple, and cost-effective solution. A simple and clear physical insight into the principle of operation of the current loop of this class of APFCs was suggested in [14]. All of the mentioned above APFCs with no input voltage sensing make use of a hidden current loop inside a DC-DC converter. The designs mainly differ in their method of realization of the transresistive feedback, PWM, and supplementary current loop control circuitry. Regardless of the implementation, however, the duty cycle programming is implemented according to the converters input port ideal average relationships and ideal modulator ramp signal. As a result, accurate current loop operation can only be attained in the Continuous Conduction Mode (CCM) under negligible current ripple conditions. In practice, however, the CCM-DCM mode changes, current ripple, and ramp carrier imperfections cause the duty cycle to deviate from the ideal relationship resulting in distortion in the average input current. The very proper average current mode three-loop APFC [15–18] achieves its control objectives by a