Efficient VLSI Architectures of Split-Radix FFT using New Distributed Arithmetic

Fast Fourier transform (FFT) has become ubiquitous in many engineering applications. Efficient algorithms are being designed to improve the architecture of FFT. Among the different proposed algorithms, split-radix FFT has shown considerable improvement in terms of reducing hardware complexity of the architecture compared to radix-2 and radix-4 FFT algorithms. New distributed arithmetic (NEDA) is one of the most used techniques in implementing multiplier-less architectures of many digital systems. This paper proposes efficient multiplier-less VLSI architectures of split-radix FFT algorithm using NEDA. As the architecture does not contain any multiplier block, reduction in terms of power, speed, and area can greatly be observed. One of the proposed architectures is designed by considering all the inputs at a time and the other is designed by considering 4 inputs at a time, the total number of inputs in both cases being 32. The proposed designs are designed using both FPGA as well as ASIC design flows. 180nm process technology is used for ASIC implementation. The results show the improvements of proposed designs compared to other architectures.