Performance Analysis of High Speed Low Power Carry Look-Ahead Adder Using Different Logic Styles

A carry look-ahead adder improves speed byreducing the amount of time required to resolve carry bits. It iswidely used in any electronic computational devices. In this papera 4 bit & 8 bit CLA has been implemented using different staticand dynamic logic styles such as Standard CMOS, DCVS PseudoNMOS, PTL & Domino logic style. The performance of the CLAhas been measured by comparing the results in terms ofpropagation delay, power dissipation and their Power DelayProduct. The simulation is done with the help of Tanner EDA toolconsidering the different feature sizes of 150nm, 200nm &250nm. Result analyses are also carried out for intrinsic andextrinsic load capacitances. This work will helpful for any circuitdesigner to build any system.