Low Power Elliptic Curve Digital Signature Design for Constrained Devices

Digital signatures represent one of the most widely used security technologies for ensuringunforgeability and non-repudiation of digital data. In this paper a reduced power dissipation ofhardware Elliptic Curve Digital Signature design has been developed.Our proposed architecture is based on the Globally Asynchronous Locally Synchronous (GALS)design methodology. In GALS system, modules that are not used frequently can be made toconsume less power by pausing their local clocks until they are needed. Our design consists ofusing units that are clocked independently. The whole ECDSA design is captured using VHDLlanguage, over the finite field GF (2163), and the Virtex IV FPGA device is used for the hardwareimplementation of the architecture.