VLSI Implementation of DWT Using Systolic Array Architecture

This work presents an implementation of DiscreteWavelet Transform (DWT)using Systolic architecture in VLSI.This architecture consist of Input delay unit, filter, register bankand control unit. This performs the calculation of high pass andlow pass coefficients by using only one multiplier. Thisarchitecture has been simulated and implemented in VLSI. Thehardware utilization efficiency is more compared to the referreddue to FBRA Scheme. The systolic nature of this architecturecorresponding to a clock speed of 115.9 MHz has its advantage inOptimizing area, time and power. The architecture is simple,modular, and cascadable for computation of one, ormulti-dimensional DWT.