VLSI Design of Pipelined R2MDC FFT for MIMO OFDM Transceivers

In this study, an area-efficient low power FFT (Fast Fourier Transform) processor is proposed for MIMO-OFDM (Multi Input Multi Output-Orthogonal Frequency Division Multiplexing) that consists of a modified architecture of radix-2 algorithm which is described as Radix-2 Multipath Delay Commutation (R2MDC). Orthogonal frequency-division multiplexing is a popular method for high-data-rate wireless transmission. OFDM may be combined with multiple antennas at both the access point and mobile terminal to increase diversity gain and/or Enhance system capacity on a time-varying multi path fading channel, resulting in a multiple-input multiple-output OFDM system. This study described the VLSI design of R2MDC FFT for high throughput MIMO OFDM transceivers targeted to future wireless LAN systems. The proposed system is pipelined Radix 2 multipath delay commutation FFT has been designed for MIMO OFDM. The MIMO OFDM transceivers have been designed according to the proposed OFDM parameters. A low-power efficient and full-pipelined architecture enables the real-time operations of MIMO OFDM transceivers. The FPGA board has been developed to verify their circuit behavior and implementation of MIMO OFDM Transceivers.