Implementation of Pipelined Architecture for Physical Downlink Channels of 3GPPLTE

LTE(Long Term Evolution) is a high data rate, low latency and packet optimized radio access technologydesigned to support roaming Internet access via cell phones and handheld devices in 3G and 4G networks.This paper mainly focuses on to improve the processing speed and decrease themaximumdelay of thedownlink channels using thepipelined buffer controlledtechnique. This paper proposesPipelined buffercontrolledArchitecture for both transmitter and receiver forPhysicalDownlink channelsof3GPP-LTE.The transmitter architecture comprises Bit Scrambling, Modulation mapping, Layer mapping, Precodingand Resource element mapping modules. The receiver architecture comprises Demapping from resourceelements, Decoding, Comparing and Detection, Delayer mapping and Descrambling modules as describedin LTE specifications.Inaddition to these,buffers are includedin both transmitter and receiverarchitectures. Modelsim is used for simulation, synthesis and implementation areachieved usingPlanAhead13.2 tool on Virtex-5, xc5vlx50tff1136-1 device board is used.Implemented results are discussedin terms ofRTL design, FPGA editor, Power estimation andResource estimation