Hardware Implementation of Efficient Modified Karatsuba Multiplier Used in Elliptic Curves

The efficiency of the core Galois field arithmetic improves theperformance of elliptic curve based public key cryptosystemimplementation. This paper describes the design and implementationof a reconfigurable Galois field multiplier, which is implementedusing field programmable gate arrays ( extbf{FPGAs}). Themultiplier of Galois field based on Karatsuba's divide and conqueralgorithm allows for reasonable speedup of the top-level publickey algorithms. Binary Karatsuba multiplier is more efficient ifit is truncated at n-bit multiplicand level and use an efficientclassic multiplier algorithm. In these work three levels totruncate Binary Karatsuba algorithm (4 bits, 8 bits and 16 bits)are chosen showing that 8 bits is the best level for minimumnumber of slices and time delay to truncate Binary Karatsubaalgorithm which is designed on an Xilinx VirtexE XCV2600 FPGAdevice. The VHDL hardware models are building using Xilinx ISEfoundation software. This work is able to compute GF(2191)multiplication in 45.889 ns. experimental results of comparingblock and stream ciphers when used to secure VoIP in terms ofend-to-end delay and subjective quality of perceived voice.