Low Read Equivalent Stress Fault Detection in CMOS SRAMs Using MARCH Algorithm

This paper outlines the reduction of Read Equivalent Stress (RES) during test of SRAM memories and demonstrates that the modified pre-charge activity reduces RES because of the predictable addressing sequence. We exploit this observation in order to show minimization of power dissipation during test by eliminating the unnecessary power consumption associated with RES .Read or write operations on a cell involve a stress on the other cells of the same word line is called Read Equivalent Stress. Read Equivalent Stress has the same effect than a read operation. We have calculated 99.8% reduction in RES with the modified pre-charge activity during test for different MARCH algorithms.