Design of a Multiplexer In Multiple Logic Styles for Low Power VLSI

The Low power and low energy has become an important issue in today’s consumer electronics. Any combinational circuit can be represented as a multiple inputs with single output. Multiplexers are used to design any digital combinational logic circuit. Hence it is required to design a multiplexer with low power consumption and high speed. The main objective of this paper is to design the multiplexer using complementary metal oxide semiconductor (CMOS) logic and pass-transistor logic styles.The power consumption, delay, area, transistor count of various logic styles are compared. This paper shows that static NMOS logic multiplexer is an optimum device level design which has characteristics of high speed with minimum power compared with other realizations. These different logic styles are compared by performing detailed transistor level simulations using CAD tools of DSCH3 and Micro wind 3.1 in submicron regime.