Hardware Implementation of Discrete Fourier Transform and its Inverse Using Floating Point Numbers

This paper concentrates on the FPGA implementation of discrete Fourier transforms (DFT) and inverse discrete Fourier transform (IDFT) based on floating point numbers. Floating point representation of the numbers support much wider range of values and achieve greater range at the expense of precision. Firstly general purpose arithmetic modules addition, subtraction, multiplier and divider based on 32 bit single precision IEEE-754 standard are designed and then DFT/IDFT algorithms architectures are implemented. The architectures of DFT and IDFT algorithms are based on radix 2 butterfly computations due to its less computation time .To reduce the required hardware resources, resource sharing scheme is used. Algorithms architectures are designed using hardware description language (VHDL), simulated using ModelSim6.6e tool and then hardware is implemented on Xilinx Virtex-5 LX110T board