The Design of FPGA Implementation of 16-Tap FIR Filter using Improved DA Algorithm

when the DA (distributed arithmetic)algorithm is directly applied in FPGA (fieldprogrammable gate array) to realize FIR (finiteimpulse response) filter, it is difficult to achieve thebest configuration in the coefficient of FIR filter, thestorage resource and the computing speed.According to this problem, the paper provides thedetailed analysis and discussion in the algorithm, thememory size and the look-up table speed. Also, thecorresponding optimization an improvementmeasures are discussed and the concrete Hardwarerealization of the circuit is presented. The designbased on Altera EP2C5T144C8 chips is synthesizedunder the integrated environment of QUARTUS II7.1. The results of Simulation and test show that thismethod greatly reduces the FPGA hardware resourceand the high speed filtering is achieved. The designhas a big breakthrough compared to the traditionalFPGA realization.