Design and Implementation of 64 Bit RISC Processor Using System on Chip (SOC)

In this paper, we present the design and implementation of a 64-bit reduced instruction set (RISC) processor with built-in-self test (BIST) features. A built-in self-test (BIST) or built-in test (BIT) is a mechanism that permits a machine to test itself. Key features of the design including its architecture, data path, and instruction set are presented. The design is implemented using VERILOG and verification is done on IUS (CADENCE) simulator. The proposed design may find applications where automation and control is required, say, in bottling plants and control of robotic movements. Illustrations highlight the typical use of our processor in bottling plants using exhaustive simulations. Future applications may include its use in vending machines, ATMs, mobile phones, and Portable gaming kits.