An Effective Leading Zero Anticipation for High Speed Floating Point Addition and Subtraction

A new leading-zero anticipatory (LZA) logic for high-speed floating-point addition and subtraction is proposed. The pre-decoding for normalization concurrently with addition for the significant is carried out in this logic. Shift operation of normalization in parallel with the rounding operation is also performed. The use of simple Boolean algebra allows the proposed logic to be constructed from a simple CMOS circuit.