Low power add and shift multiplier design using BZFAD architecture

A multiplier is one of the key hardware blocks in most digital and high performance systems such as FIR filters, digital signal processors and microprocessors etc. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following- high speed, low power consumption, regularity of layout and hence less area or even combination of them in multiplier. Thus making them suitable for various high speed, low power and compact VLSI implementations. However area and speed are two conflicting constraints. So improving speed results always in larger areas. So here we try to find out the best trade off solution among them. Generally as we know multiplication goes in two basic steps. Partial product and then addition. Hence here, we first try to design different adders and compare their speed and complexity of circuit i.e. the area occupied. Considering the design of Wallace tree multiplier then followed by Booth’s Wallace multiplier and comparing the speed and Power consumption in them.