SIMULATIVE INVESTIGATIONS OF DDR2 (SDRAM) MODEL IN HDL

This paper presents a simulation based implementation of DDR2 memory model in HDL language. The study covers single data rate, double data rate and their comparisons. This model consists of five blocks i.e. Instruction decoder, DDR2 interface, SRAM interface, bank control and adder reorder. This work is evaluated using Xilinx 12.4 ISE and ISIM is used for simulation.