DESIGN OF LOW POWER LOW NOISE BIQUAD GIC NOTCH FILTER IN 0.18 μM CMOS TECHNOLOGY

In design of analog circuits not only the gain and speed are important but power dissipation, supply voltage, linearity, noise and maximum voltage swing are also important. In this paper a biquad GIC notch filter is design which provides low power. In this research, the design and VLSI implementation of active analog filter, based on the Generalized Impedance Converter (GIC) circuit, are presented [1]. The circuit is then modeled and simulated using the Cadence Design Tools software package. Active filters are implemented using a combination of passive and active (amplifying) components, and require an outside power source. Operational amplifiers are frequently used in active filter designs. These can have high Q factor, and can achieve resonance without the use of inductors. This paper presents a new biquad GIC notch filter topology for image rejection in heterodyne receivers and Front End receiver applications. The circuit contains two op-amp, resistor, capacitor topology for testing purposes. It is implemented with standard CMOS 0.18μm technology. The circuit consumes 0.54 mW of power with a open loop gain 0dB, 1 dB compression point the linear gain obtained +7.5dBm at 1.1 kHz and 105 degree phase response from a 1.8V power supply optimum [2].