POWER ESTIMATION ANALYSIS FOR CMOS CELL STRUCTURES

Increasing demand for portable electronics for computing and communication, as well as other applications, has necessitated longer battery life, lower weight, and lower power consumption. In order to satisfy these requirements, research activities focusing on low power/low voltage design techniques are underway. Since 'power' is now one of the design decision variables, the expanded design space required for low power has further increased the complexity of an already non-trivial task. Low power design basically involves two concomitant tasks: power estimation and analysis and power minimization. These tasks need to be carried out at each of the levels in the design hierarchy, namely, the behavioral, architectural, logic, circuit and physical levels. In this survey of the current state of the field, many of the salient power estimation and minimization techniques proposed for low power VLSI design are reviewed. In this paper comparison of power estimation of various basic CMOS cell structures on various technologies (TSMC 0.35um, TSMC 0.2um and TSMC 0.18um) is carried out. The research issues in order to make the low power design are also discussed in the paper. The paper is organized as follows: First, the sources of power dissipation in CMOS circuits and degrees of freedom in the low power design space are described in section-2. In section-3 various power minimization techniques are discussed. Designing of various CMOS cells and Simulation results are shown in section-4&5.Athe end of the paper conclusion is given. We have used IC Design studio, HEP2 module from Mentor Graphics to obtain the simulation for various analysis of power estimation.