DESIGN OF LOW POWER PHASE LOCKED LOOP IN SUBMICRON TECHNOLOGY

This paper presents design of phase locked loop systemfor low power applications. The design focuses on reducingpower consumption. This design consists of low powerphase frequency detector, low jitter charge pump, fully differentialRing oscillator based VCO along with voltage to currentconvertor and current controlled oscillator, 2nd orderpassive loop filter and 7 bit digital frequency divider using350nm, 180nm and 130nm technology nodes at 350MHz.Results are carried out on SPICE at various technologynodes. For 3V power supply, power consumption of PLLsystem is reduced to 65% at 350nm technology node.