Modified Area Efficient Carry Select Adder (MA-CSLA)

Carry Select adder (CSLA) is an adder which computes n+1 bit sum of two n bit numbers. When compared to earlier Ripple Carry Adder and Carry Look Ahead Adder, Regular CSLA(R-CSLA)is observed to provide optimized results in terms of area[1]. From the architecture of Modified CSLA[2] it is observed that there is a possibility of reducing the area further .Regular CSLA uses dual Ripple Carry Adder to perform addition operation. Modified CSLA(M-CSLA) uses BEC as add one circuit which reduces the area furthermore, such that the total gate count is reduced subsequently. For 16bit addition in this paper,it is proposed to simple gate level modification which significantly reduces the area by 34% when compared with R-CSLA and 15% when compared to M-CSLA .It is known as Modified Area Efficient Carry Select Adder(MA-CSLA). The strategic work in MA-CSLA reduces the area using the modified XOR gates. The result analysis shows that the Modified area efficient CSLA is better than the M-CSLA for low power applications like digital signal processing, ALU.