Performance based Configuration and implementation of Hash Processor

Extraordinary developments in the wired and wireless communications area, the requisition for secure data transmission increases. In order to find solutions for this increasing requisition new algorithms and security standards are developed. Among these algorithms and standards, hash functions are mainly used. In this paper design and implementation of an FPGA based hash processor is described. The proposed hash processor consists of an arithmetic logic unit, a message computation block, a constants ROM, a register file, a programmable control unit, program memory and standard UART serial interface. Hash processor is configured by the instructions in the program memory and supports SHA-1. The hardware is described in VHDL and verified on Xilinx FPGAs.