A Novel Architecture of SRAM Cell for Low-Power Application

Low-power Random Access Memory (RAM) has seen a remarkable and rapid progress in power reduction. Many circuit techniques for active and standby power reduction in static and dynamic RAMS have been devised. This paper presents a new static random access memory (SRAM) cell. The proposed SRAM cell uses two trapezoidal-wave pulses and resembles behavior of static CMOS 4T-SRAM. The elementary cell structure of proposed SRAM cell consists of two high load resistors which are constructed of PMOS, and NMOS switch which is necessary to restrict short circuit current. From the simulation results, we show that the energy consumption of the proposed circuit is lower than that of conventional SRAM cell.