A High Bit Rate Serial-Serial Multiplier

A design of serial-serial hybrid multiplier is proposed for applications with high data rate. Here the proposed technique effectively forms the entire partial product rows in just n cycles where as conventional serialserial multipliers take 2n cycles to form all partial products. The conventional way of partial product formation is rearranged here. Here the proposed architecture achieves high data rate by replacing full adders with asynchronous 1’s counter so that critical path is limited to only DFF and an AND gate. The use of asynchronous counter reduces the height of the partial product rows from n to [log2n]+1, resulting in reduction of complex adder tree. The proposed multiplier consists of serial-serial data accumulation unit followed by a dadda multiplier which reduces the average power dissipation. It has a small delay penalty to complete a multiplication when compared to a conventional parallel array multiplier.