FPGA Based Design and Implementation of Efficient Video Filter

In this paper an efficient design and implementation of ITU-R BT.601 video filter has been presented for digital television receivers. The proposed video filter has been realized using MAC algorithm. The implementation is based on efficient utilization of embedded multipliers and look up table (LUT) of the target device to improve speed, area efficiency and power consumption. It is an efficient method because the use of embedded resources not only increases the speed but also saves the general purpose resources of the target device. The proposed video filter has been designed and simulated using Matlab, synthesized with Xilinx Synthesis Tool (XST), and implemented on Spartan 3E based 3s500efg320-5 FPGA device. The developed video filter structure can operate at an estimated frequency of 28.758 MHz by utilizing 12 multipliers and 245 LUTS of target FPGA device to provide cost effective solution for mobile and wireless communication systems.