A Novel Coarse-to-fine Search Motion Estimator

This study presents a new block matching motion estimation and its VLSI architecture design. The proposed Candidate Block and Pixel Sub-sampling (CBPS) algorithm reduces the number of candidate blocks selected to 5x(2p+1) against (2p+1)2 in case of FSBMA. A new 4-queen pattern for pixel sub-sampling is also introduced. Our basic aim is to reduce the overall computations, so as to make data flow more regular and suitable for hardware. The loss in PSNR is very negligible from frame to frame and at the worst case, comes to 0.23 dB. The speed up factor achieved is 13.6. Computational complexity is reduced to 5.25%. We propose an architecture that is composed of a single PE and an adder to efficiently compute Sub-sampled Sum of Absolute Difference (SSAD). Also a modified search criteria called Reduced Bit Sub-sampled Sum of Absolute Difference (RBSSAD) is introduced. Simulation results show that our design is much more area and power efficient than many full search architectures, while maintaining good video quality and processing capability.