We present copper structures composed of multilayer, stacked inductors (MLSIs) with tens of micro-Henry inductance for use in low frequency (sub 100？MHz), power converter technology. Unique to this work is the introduction of single-level lithography over the traditional two-level approach to create each inductor layer. The result is a simplified fabrication process which results in a reduction in the number of lithography steps per inductor (metal) layer and a reduction in the necessary alignment precision. Additionally, we show that this fabrication process yields strong adhesion amongst the layers, since even after a postprocess abrasion technique at the inner diameter of the inductors, no shearing occurs and connectivity is preserved. In total, three separate structures were fabricated using the single-level lithography approach, each with a three-layered, stacked inductor design but with varied geometries. Measured values for each of the structures were extracted, and the following results were obtained: inductance values of 24.74, 17.25, and 24.74？μH, self-resonances of 9.87, 5.72, and 10.58？MHz, and peak quality factors of 2.26, 2.05, and 4.6, respectively. These values are in good agreement with the lumped parameter model presented. 1. Introduction Over the last decade, researchers have done a considerable amount of work to model, characterize, and design air-core spiral inductors on silicon technology for both radio-frequency integrated circuits (RFIC) and monolithic microwave integrated circuits (MMICs). In most of these works, both performance and cost are typical issues examined. For many designers, performance relates directly to improving the quality factor of these spiral inductors. Most notably, this has been achieved using designs such as multilayered, stacked inductors (MLSIs), see Figure 1, which increase the inductance value due to the mutual magnetic coupling [1], and multiple shunt inductors, which lower the resistance [2, 3]. For those researchers concerned with cost, much of the focus is within analyzing the process with respect to the standard complementary metal oxide semiconductor (CMOS) technology, where the key factors in determining the cost are (1) feature size, (2) number and kinds of layers, and (3) chip area occupied [4]. Within this work, we focus on simplifying the fabrication of integrated inductors for the emerging area of power converter technology. Specifying for this growing field, researchers must again balance performance and cost issues with new requirements like the need for much higher inductance in the
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