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Thread Synchronization: From Mutual Exclusion to Transactional MemoryKeywords: Hardware accelerated STM , Hardware transactional memory , Hybrid transactional memory , Mutual exclusion , Non-blocking synchronization , Thread synchronization , Transactional memory , Software transactional memory. Abstract: Transactional memory (TM) is being viewed by researchers as a suitable mechanism to perform shared-memory synchronization on upcoming many-core systems. This paper provides an introductory material on TM, followed by a background of important historical work on synchronization leading to current TM research. The paper reviews recent pure hardware and hardware-software TM design proposals, and finally brings out a list of interesting open problems in this field.
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