Spacer Optimization and Accurate Small-Signal Modeling of 90nm Gate Underlap SOI-MOSFETs for Low Power GHz Applications

This paper presents the significance of gate-source/drain extension region (also known as underlap design) optimization in 90nm single gate (SG) Silicon-on-Insulator (SOI) MOSFET for low power GHz frequency applications. Using an optimal spacer s ( 0.8×LG, where LG is gate length), it has been found that the device exhibits intrinsic gain of 25 dB in low-moderate inversion region (VOD =VGS – VTH ≤ 90 mV, where VOD, VGS and VTH are the overdrive, gate and threshold voltages, respectively) at operating frequency of 20 GHz. An accurate (including non-quasi-static and extrinsic parasitics effects) small-signal model for the optimized device has been presented. The comparison of Y-parameters of 2D ATLAS with overall modeled value (up to 20 GHz) has shown an excellent matching (with an average error of ≤5%), whereas results from quasi-static (QS) predictive technology model (PTM) differ significantly (>20%). Optimized underlap device shows transit frequency fT and maximum frequency of oscillation fMAX, ~108 and ~130 GHz respectively, with noise figure (NF) ~2.8 dB and exhibits unilateral power gain (ULG) ~38 dB (VOD =90mV, drain-to-source current IDS 0.64mA and drain-to-source voltage VDS = 1V) at 20 GHz. Comparison with limited measured data suggest that simulated results are in well conformity, which suggest the possibility of use of underlap device technology in the design of key blocks such as low noise amplifier LNA and mixer for GHz applications. Key Words: Gate Underlap, silicon-on-Insulator, Non-Quasi-Static, Transconductance-to-Net-Charge Ratio (TCR), Low Power.