Design of Double Gate Vertical MOSFET using Silicon On Insulator (SOI) Technology

Application of symmetric double gate vertical metal oxide semiconductorfield effect transistors (MOSFETs) is hindered by the parasitic overlapcapacitance associated with their layout, which is considerably larger than fora lateral MOSFET on the same technology node. A simple processsimulation has been developed to reduce the parasitic overlap capacitance inthe double gate vertical MOSFETs by using SOI (Silicon on Insulator) inbottom planar surfaces side. The result shows that while channel lengthdecreases, the threshold voltage goes lower, the DIBL rises and subthresholdswing tends to decrease, for both structures. It is noted that the SOI DGVMOSFET structure generally have better performance in SCE controlcompared to bulk vertical MOSFET. The presence of buried oxide is believed to increase the performance of vertical MOSFET, essentially incontrolling the depletion in subthreshold voltage