Design and Development of Scalable FFT Architecture for Filter Bank De-multiplexing Application

This paper proposes a high speed FFT implementation based on Radix-22 single path delay feedback pipelined structure which was implemented on an FPGA. The radix-22 algorithm is used to decrease the number of non trivial multiplication. The number of multiplication needed for calculating the FFT by this algorithm is same as that of radix-4 but its butterfly structure is equivalent to that of radix-2. The simple radix-2 structure helps in efficient VLSI implementation. The single path delay feedback structure is used for the implementation of the algorithm to make it pipelined, which is a part of the filter bank architecture for satellite application.