CO-SIMULATION OF SYSTEMC WITH SYSTEM VERILOG: A VCS TOOL APPROACH

Due to increased complexity of SoC designs, the importance of design reuse, verification, and debugging increased. Theoretically these concepts seem simple and easy to implement, but there are number of challenges that design and verification team must address while practical implementation. For example, one of the significant barriers to IP reuse is the wide variety of design languages used in IP design and verification. Some of the commonly used languages for design and verification are SystemVerilog, SystemC and conventional HDL languages such as Verilog and VHDL. These languages have their unique strengths which make them more suitable for writing certain portions of a design or IP. But for design to be successful, all of its individual components must communicate with each other which are in the different languages. This paper provides guidelines and ways of how to communicate with SystemVerilog and SystemC. It describes different approaches and provides useful insights to help users to integrates IP blocks in a SystemVerilog environment.